Start: Tuesday, 11 February 2020 @ 08:00

End: Thursday, 13 February 2020 @ 15:00

Description:

With the increasing prevalence of multicore processors, shared-memory programming models are essential. OpenMP is a popular, portable, widely supported, and easy-to-use shared-memory model.

Since its advent in 1997, the OpenMP programming model has proved to be a key driver behind parallel programming for shared-memory architectures.  Its powerful and flexible programming model has allowed researchers from various domains to enable parallelism in their applications.  Over the more than two decades of its existence, OpenMP has tracked the evolution of hardware and the complexities of software to ensure that it stays as relevant to today’s high performance computing community as it was in 1997.

This workshop will cover a wide range of  topics, reaching from the basics of OpenMP programming using the Parallelware tools to really advanced topics.

Day 1

The first day will cover basic parallel programming with OpenMP on CPUs and GPUs using the Parallelware Trainer Software by Appentra Solutions (https://www.appentra.com/products/parallelware-trainer/). Appentra’s Parallelware tools are based on over 10 years of research by co-founder and CEO, Dr. Manuel Arenaz, who will be the lecturer of the first day. Parallelware  enables the identification of opportunities for parallelization and the provision of appropriate parallelization methods using state-of-the-art industrial standards. Parallelware Trainer was developed specifically to help improve the experience of HPC training, providing an interactive learning environment that uses examples that are the same or similar to real codes. Parallelware Trainer provides support for OpenMP (including multi-threading, offloading and tasking) and OpenACC (for offloading), providing users with the opportunity to use GPU services with either OpenMP or OpenACC.

Day 2 and 3

Day 2 and 3 will cover advanced topics like (partly still to be confirmed):

Mastering Tasking with OpenMP
Host Performance
NUMA Aware Programming, Thread Affinity
Vectorization / SIMD
Tool support for Performance and Correctness
OpenMP for Heterogeneous Computing
OpenMP 5.0 Features and Future Roadmap

Developers usually find OpenMP easy to learn. However, they are often disappointed with the performance and scalability of the resulting code. This disappointment stems not from shortcomings of OpenMP but rather with the lack of depth with which it is employed. The lectures on Day 2 and Day 3 will address this critical need by exploring the implications of possible OpenMP parallelization strategies, both in terms of correctness and performance.

We cover tasking with OpenMP and host performance, putting a focus on performance aspects, such as data and thread locality on NUMA architectures, false sharing, and exploitation of vector units. Also tools for performance and correctness will be presented.

Current trends in hardware bring co-processors such as GPUs into the fold. A modern platform is often a heterogeneous system with CPU cores, GPU cores, and other specialized accelerators. OpenMP has responded by adding directives that map code and data onto a device, the target directives. We will also explore these directives as they apply to programming GPUs.

Finally, OpenMP 5.0 features will be highlighted and the future roadmap of OpenMP will be presented.

All topics are accompanied with extensive case studies and we discuss the corresponding language features in-depth.

A detailled agenda of the course will be provided later. Topics might be still subject to change.

For the hands-on sessions participants need to bring their own laptops with an ssh-client installed.

The course is organized as a PRACE training event by LRZ in collaboration with Appentra Solutions, Intel and RWTH Aachen.

Lecturers

Dr. Manuel Arenaz is CEO at Appentra Solutions and professor of computer science at the University of A Coruña (Spain). Holds a PhD on advanced compiler techniques for automatic parallelization of scientific codes. After 10+ years teaching parallel programming at undergraduate and PhD levels, he strongly believes that the next generation of STEM engineers needs to be educated in HPC technologies to address the digital revolution challenge. Recently, he co-founded Appentra Solutions to commercialize products and services that take advantage of Parallware, a new technology for semantic analysis of scientific HPC codes.

Dr. Reinhold Bader studied physics and mathematics at the Ludwigs-Maximilians University in Munich, completing his studies with a PhD in theoretical solid-state physics in 1998. Since the beginning of 1999, he has worked at Leibniz Supercomputing Centre (LRZ) as a member of the scientific staff. He is currently group leader of the HPC services group at LRZ, which is responsible for operation of all HPC-related systems and system software packages at LRZ. Reinhold also participates in the standardisation activities of the Fortran programming language in the international workgroup WG5

Dr.  Michael Klemm holds an M.Sc.  and a Doctor of Engineering degree from the Friedrich-Alexander-University Erlangen-Nuremberg, Germany.  Michael Klemm is a Principal Engineer in the Compute Ecosystem Engineering organization of the Intel Architecture, Graphics, and Software group at Intel in Germany.  His areas of interest include compiler construction, design of programming languages, parallel programming, and performance analysis and tuning.  Michael Klemm joined the OpenMP organization in 2009 and was appointed CEO of the OpenMP ARB in 2016.

Dr. Christian Terboven is a senior scientist and leads the HPC group at RWTH Aachen University. His research interests center around Parallel Programming and related Software Engineering aspects. Dr. Terboven has been involved in the Analysis, Tuning and Parallelization of several large-scale simulation codes for various architectures. He is responsible for several research projects in the area of programming models and approaches to improve the productivity and efficiency of modern HPC systems.

Dr. Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is education and training coordinator at LRZ. Since 2019 he is LRZ representative in the OpenMP ARB and language committee.

 

 
https://events.prace-ri.eu/event/947/

Event type:
  • Workshops and courses
OpenMP Programming Workshop @ LRZ https://tess.elixir-europe.org/events/openmp-programming-workshop-lrz With the increasing prevalence of multicore processors, shared-memory programming models are essential. OpenMP is a popular, portable, widely supported, and easy-to-use shared-memory model. Since its advent in 1997, the OpenMP programming model has proved to be a key driver behind parallel programming for shared-memory architectures.  Its powerful and flexible programming model has allowed researchers from various domains to enable parallelism in their applications.  Over the more than two decades of its existence, OpenMP has tracked the evolution of hardware and the complexities of software to ensure that it stays as relevant to today’s high performance computing community as it was in 1997. This workshop will cover a wide range of  topics, reaching from the basics of OpenMP programming using the Parallelware tools to really advanced topics. Day 1 The first day will cover basic parallel programming with OpenMP on CPUs and GPUs using the Parallelware Trainer Software by Appentra Solutions (https://www.appentra.com/products/parallelware-trainer/). Appentra’s Parallelware tools are based on over 10 years of research by co-founder and CEO, Dr. Manuel Arenaz, who will be the lecturer of the first day. Parallelware  enables the identification of opportunities for parallelization and the provision of appropriate parallelization methods using state-of-the-art industrial standards. Parallelware Trainer was developed specifically to help improve the experience of HPC training, providing an interactive learning environment that uses examples that are the same or similar to real codes. Parallelware Trainer provides support for OpenMP (including multi-threading, offloading and tasking) and OpenACC (for offloading), providing users with the opportunity to use GPU services with either OpenMP or OpenACC. Day 2 and 3 Day 2 and 3 will cover advanced topics like (partly still to be confirmed): Mastering Tasking with OpenMP Host Performance NUMA Aware Programming, Thread Affinity Vectorization / SIMD Tool support for Performance and Correctness OpenMP for Heterogeneous Computing OpenMP 5.0 Features and Future Roadmap Developers usually find OpenMP easy to learn. However, they are often disappointed with the performance and scalability of the resulting code. This disappointment stems not from shortcomings of OpenMP but rather with the lack of depth with which it is employed. The lectures on Day 2 and Day 3 will address this critical need by exploring the implications of possible OpenMP parallelization strategies, both in terms of correctness and performance. We cover tasking with OpenMP and host performance, putting a focus on performance aspects, such as data and thread locality on NUMA architectures, false sharing, and exploitation of vector units. Also tools for performance and correctness will be presented. Current trends in hardware bring co-processors such as GPUs into the fold. A modern platform is often a heterogeneous system with CPU cores, GPU cores, and other specialized accelerators. OpenMP has responded by adding directives that map code and data onto a device, the target directives. We will also explore these directives as they apply to programming GPUs. Finally, OpenMP 5.0 features will be highlighted and the future roadmap of OpenMP will be presented. All topics are accompanied with extensive case studies and we discuss the corresponding language features in-depth. A detailled agenda of the course will be provided later. Topics might be still subject to change. For the hands-on sessions participants need to bring their own laptops with an ssh-client installed. The course is organized as a PRACE training event by LRZ in collaboration with Appentra Solutions, Intel and RWTH Aachen. Lecturers Dr. Manuel Arenaz is CEO at Appentra Solutions and professor of computer science at the University of A Coruña (Spain). Holds a PhD on advanced compiler techniques for automatic parallelization of scientific codes. After 10+ years teaching parallel programming at undergraduate and PhD levels, he strongly believes that the next generation of STEM engineers needs to be educated in HPC technologies to address the digital revolution challenge. Recently, he co-founded Appentra Solutions to commercialize products and services that take advantage of Parallware, a new technology for semantic analysis of scientific HPC codes. Dr. Reinhold Bader studied physics and mathematics at the Ludwigs-Maximilians University in Munich, completing his studies with a PhD in theoretical solid-state physics in 1998. Since the beginning of 1999, he has worked at Leibniz Supercomputing Centre (LRZ) as a member of the scientific staff. He is currently group leader of the HPC services group at LRZ, which is responsible for operation of all HPC-related systems and system software packages at LRZ. Reinhold also participates in the standardisation activities of the Fortran programming language in the international workgroup WG5 Dr.  Michael Klemm holds an M.Sc.  and a Doctor of Engineering degree from the Friedrich-Alexander-University Erlangen-Nuremberg, Germany.  Michael Klemm is a Principal Engineer in the Compute Ecosystem Engineering organization of the Intel Architecture, Graphics, and Software group at Intel in Germany.  His areas of interest include compiler construction, design of programming languages, parallel programming, and performance analysis and tuning.  Michael Klemm joined the OpenMP organization in 2009 and was appointed CEO of the OpenMP ARB in 2016. Dr. Christian Terboven is a senior scientist and leads the HPC group at RWTH Aachen University. His research interests center around Parallel Programming and related Software Engineering aspects. Dr. Terboven has been involved in the Analysis, Tuning and Parallelization of several large-scale simulation codes for various architectures. He is responsible for several research projects in the area of programming models and approaches to improve the productivity and efficiency of modern HPC systems. Dr. Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is education and training coordinator at LRZ. Since 2019 he is LRZ representative in the OpenMP ARB and language committee.     https://events.prace-ri.eu/event/947/ 2020-02-11 08:00:00 UTC 2020-02-13 15:00:00 UTC [] [] [] workshops_and_courses [] []